| IntAct: A 96-core processor with six chiplets 3D-stacked on an active interposer with distributed interconnects and integrated power management P Vivet, E Guthmuller, Y Thonnart, G Pillonnet, C Fuguet, I Miro-Panades, ... IEEE Journal of Solid-State Circuits 56 (1), 79-97, 2020 | 68 | 2020 |
| 2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm … P Vivet, E Guthmuller, Y Thonnart, G Pillonnet, G Moritz, I Miro-Panadès, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 46-48, 2020 | 64 | 2020 |
| Active interposer technology for chiplet-based advanced 3D system architectures P Coudrain, J Charbonnier, A Garnier, P Vivet, R Vélard, A Vinci, ... 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 569-578, 2019 | 55 | 2019 |
| POPSTAR: A robust modular optical NoC architecture for chiplet-based 3D integrated systems Y Thonnart, S Bernabé, J Charbonnier, C Bernard, D Coriat, C Fuguet, ... 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2020 | 31 | 2020 |
| WAVES: Wavelength selection for power-efficient 2.5 D-integrated photonic NoCs A Narayan, Y Thonnart, P Vivet, CF Tortolero, AK Coskun 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 516-521, 2019 | 22 | 2019 |
| Exanode: combined integration of chiplets on active interposer with bare dice in a multi-chip-module for heterogeneous and scalable high performance compute nodes PY Martinez, Y Beilliard, M Godard, D Danovitch, D Drouin, J Charbonnier, ... 2020 IEEE Symposium on VLSI Technology, 1-2, 2020 | 9 | 2020 |
| A 29 Gops/Watt 3D-ready 16-core computing fabric with scalable cache coherent architecture using distributed L2 and adaptive L3 caches E Guthmuller, C Fuguet, P Vivet, C Bernard, I Miro-Panades, J Durupt, ... ESSCIRC 2018-IEEE 44th European Solid State Circuits Conference (ESSCIRC …, 2018 | 7 | 2018 |
| Accelerating variants of the conjugate gradient with the variable precision processor Y Durand, E Guthmuller, C Fuguet, J Fereyre, A Bocco, R Alidori 2022 IEEE 29th Symposium on Computer Arithmetic (ARITH), 51-57, 2022 | 6 | 2022 |
| Storage class memory with computing row buffer: A design space exploration V Egloff, JP Noel, M Kooli, B Giraud, L Ciampolini, R Gauchi, C Fuguet, ... 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2021 | 6 | 2021 |
| Trace-driven exploration of sharing set management strategies for cache coherence in manycores J Dumas, E Guthmuller, CF Tortolero, F Pétrot 2017 15th IEEE International New Circuits and Systems Conference (NEWCAS), 77-80, 2017 | 5 | 2017 |
| A method for fast evaluation of sharing set management strategies in cache coherence protocols J Dumas, E Guthmuller, C Fuguet Tortolero, F Pétrot Architecture of Computing Systems-ARCS 2017: 30th International Conference …, 2017 | 2 | 2017 |
| C. Fuguet T.,“Porting the Linux kernel to the TSAR manycore architecture” J Porquet, A Greiner Design, Automation and Test in Europe University Booth (DATE), 2015 | 2 | 2015 |
| Pascal Vivet, César Fuguet Tortolero, and Ayse K Coskun. 2019. WAVES: Wavelength selection for power-efficient 2.5 D-integrated photonic NoCs A Narayan, Y Thonnart Design, Automation & Test in Europe Conference & Exhibition (DATE), 516-521, 0 | 2 | |
| HPDcache: Open-source high-performance L1 data cache for RISC-V cores C Fuguet Proceedings of the 20th ACM International Conference on Computing Frontiers …, 2023 | 1 | 2023 |
| A Programmable Inbound Transfer Processor for Active Messages in Embedded Multicore Systems Y Durand, C Bernard, R Lemaire, CF Tortolero, E Garat 2017 Euromicro Conference on Digital System Design (DSD), 192-197, 2017 | 1 | 2017 |
| Introduction of Fault-Tolerance Mechanisms for Permanent Failures in Coherent Shared-Memory Many-Core Architectures CF Tortolero Université Pierre et Marie Curie-Paris VI, 2015 | 1 | 2015 |
| Xvpfloat: RISC-V ISA Extension for Variable Extended Precision Floating Point Computation E Guthmuller, C Fuguet, A Bocco, J Fereyre, R Alidori, I Tahir, Y Durand IEEE Transactions on Computers, 2024 | | 2024 |
| 128-bit Addresses for the Masses (of Memory and Devices) M Bacou, A Chader, C Deshpande, C Fabre, CF Tortolero, P Michaud, ... HotInfra 2023-Workshop on Hot Topics in System Infrastructure, 2023 | | 2023 |
| Functional Verification Strategy for an Open-Source High-Performance L1 Data-Cache for RISC-V cores T Khandelwal, L Pion, C Fuguet, A Evans RISC-V Summit 2023, 2023 | | 2023 |
| Towards simulation of an unified address space for 128-bit massively parallel computers E Tomasi, C Fuguet, C Fabre, F Pétrot RISC-V Summit Europe 2023, 2023 | | 2023 |
