Vladimir Herdt
Vladimir Herdt
Senior Researcher at University of Bremen / DFKI GmbH
Email confirmado em uni-bremen.de
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Verifying SystemC using an intermediate verification language and symbolic simulation
HM Le, D Große, V Herdt, R Drechsler
Proceedings of the 50th Annual Design Automation Conference, 1-6, 2013
542013
Extensible and configurable RISC-V based virtual prototype
V Herdt, D Groβe, HM Le, R Drechsler
2018 Forum on Specification & Design Languages (FDL), 5-16, 2018
362018
Verifying SystemC using intermediate verification language and stateful symbolic simulation
V Herdt, HM Le, D Große, R Drechsler
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
262018
Compiled symbolic simulation for SystemC
V Herdt, HM Le, D Große, R Drechsler
Proceedings of the 35th International Conference on Computer-Aided Design, 1-8, 2016
242016
RISC-V based virtual prototype: An extensible and configurable platform for the system-level
V Herdt, D Große, P Pieper, R Drechsler
Journal of Systems Architecture 109, 101756, 2020
202020
Verifying Instruction Set Simulators using Coverage-guided Fuzzing*
V Herdt, D Große, HM Le, R Drechsler
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 360-365, 2019
202019
Early Concolic Testing of Embedded Binaries with Virtual Prototypes: A RISC-V Case Study*
V Herdt, D Große, HM Le, R Drechsler
2019 56th ACM/IEEE Design Automation Conference (DAC), 1-6, 2019
182019
Verifying SystemC using stateful symbolic simulation
V Herdt, HM Le, R Drechsler
2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2015
172015
Towards early validation of firmware-based power management using virtual prototypes: A constrained random approach
V Herdt, HM Le, D Große, R Drechsler
2017 Forum on Specification and Design Languages (FDL), 1-8, 2017
162017
Towards formal verification of real-world SystemC TLM peripheral models-a case study
HM Le, V Herdt, D Große, R Drechsler
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2016
152016
Early SoC security validation by VP-based static information flow analysis
M Hassan, V Herdt, HM Le, D Große, R Drechsler
2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 400-407, 2017
142017
Data flow testing for virtual prototypes
M Hassan, V Herdt, HM Le, M Chen, D Große, R Drechsler
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
132017
Towards Specification and Testing of RISC-V ISA Compliance
V Herdt, D Große, R Drechsler
2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 995-998, 2020
112020
On the Application of Formal Fault Localization to Automated RTL-to-TLM Fault Correspondence Analysis for Fast and Accurate VP-Based Error Effect Simulation: A Case Study
V Herdt, HM Le, D Große, R Drechsler
Languages, Design Methods, and Tools for Electronic System Design, 39-57, 2018
102018
ParCoSS: efficient parallelized compiled symbolic simulation
V Herdt, HM Le, D Große, R Drechsler
International Conference on Computer Aided Verification, 177-183, 2016
102016
Closing the RISC-V Compliance Gap: Looking from the Negative Testing Side*
V Herdt, D Große, R Drechsler
2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020
92020
Enhanced Virtual Prototyping: Featuring RISC-V Case Studies
V Herdt, D Große, R Drechsler
Springer Nature, 2020
82020
Fast and Accurate Performance Evaluation for RISC-V using Virtual Prototypes*
V Herdt, D Große, R Drechsler
2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 618-621, 2020
82020
Towards fully automated TLM-to-RTL property refinement
V Herdt, HM Le, D Große, R Drechsler
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018
82018
Verification of embedded binaries using coverage-guided fuzzing with SystemC-based virtual prototypes
V Herdt, D Große, J Wloka, T Güneysu, R Drechsler
Proceedings of the 2020 on Great Lakes Symposium on VLSI, 101-106, 2020
72020
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