Sandip Ray
Sandip Ray
Professor, Department of Electrical and Computer Engineering, University of Florida at Gainesville
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The changing computing paradigm with internet of things: A tutorial introduction
S Ray, Y Jin, A Raychowdhury
IEEE Design & Test 33 (2), 76-96, 2016
A survey of hybrid techniques for functional verification
J Bhadra, MS Abadir, LC Wang, S Ray
IEEE Design & Test of Computers 24 (2), 112-122, 2007
Internet-of-Things security and vulnerabilities: Taxonomy, challenges, and practice
K Chen, S Zhang, Z Li, Y Zhang, Q Deng, S Ray, Y Jin
Journal of Hardware and Systems Security 2 (2), 97-110, 2018
Post-quantum lattice-based cryptography implementations: A survey
H Nejatollahi, N Dutt, S Ray, F Regazzoni, I Banerjee, R Cammarota
ACM Computing Surveys (CSUR) 51 (6), 1-41, 2019
Efficient trace signal selection using augmentation and ILP techniques
K Rahmani, P Mishra, S Ray
Fifteenth international symposium on quality electronic design, 148-155, 2014
Verification condition generation via theorem proving
J Matthews, JS Moore, S Ray, D Vroon
International Conference on Logic for Programming Artificial Intelligence …, 2006
Challenges and trends in modern SoC design verification
W Chen, S Ray, J Bhadra, M Abadir, LC Wang
IEEE Design & Test 34 (5), 7-22, 2017
A flexible architecture for systematic implementation of SoC security policies
A Basak, S Bhunia, S Ray
2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 536-543, 2015
Post-silicon validation in the soc era: A tutorial introduction
P Mishra, R Morad, A Ziv, S Ray
IEEE Design & Test 34 (3), 68-92, 2017
Can't see the forest for the trees: State restoration's limitations in post-silicon trace signal selection
S Ma, D Pal, R Jiang, S Ray, S Vasudevan
2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2015
Efficient execution in an automated reasoning environment
DA Greve, M Kaufmann, P Manolios, JS Moore, S Ray, JL Ruiz Reina, ...
Journal of Functional Programming, 18 (1), 15-46., 2008
System-on-chip platform security assurance: Architecture and validation
S Ray, E Peeters, MM Tehranipoor, S Bhunia
Proceedings of the IEEE 106 (1), 21-37, 2017
Security assurance for system-on-chip designs with untrusted IPs
A Basak, S Bhunia, T Tkacik, S Ray
IEEE Transactions on Information Forensics and Security 12 (7), 1515-1528, 2017
Deductive verification of pipelined machines using first-order quantification
S Ray, WA Hunt
International Conference on Computer Aided Verification, 31-43, 2004
Correctness and security at odds: post-silicon validation of modern SoC designs
S Ray, J Yang, A Basak, S Bhunia
Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015
Optimizing equivalence checking for behavioral synthesis
K Hao, F Xie, S Ray, J Yang
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010
Scalable techniques for formal verification
S Ray
Springer Science & Business Media, 2010
Exploiting design-for-debug for flexible SoC security architecture
A Basak, S Bhunia, S Ray
2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2016
Formal verification for high-assurance behavioral synthesis
S Ray, K Hao, Y Chen, F Xie, J Yang
International Symposium on Automated Technology for Verification and …, 2009
Integrating external deduction tools with ACL2
M Kaufmann, JS Moore, S Ray, E Reeber
Journal of Applied Logic 7 (1), 3-25, 2009
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