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Kwangok Jeong
Kwangok Jeong
Verified email at samsung.com
Title
Cited by
Cited by
Year
32nm 1-D regular pitch SRAM bitcell design for interference-assisted lithography
RT Greenway, K Jeong, AB Kahng, CH Park, JS Petersen
Photomask Technology 2008 7122, 528-539, 2008
862008
An MTCMOS design methodology and its application to mobile computing
HS Won, KS Kim, KO Jeong, KT Park, KM Choi, JT Kong
Proceedings of the 2003 international symposium on Low power electronics and …, 2003
802003
Impact of guardband reduction on design outcomes: A quantitative approach
K Jeong, AB Kahng, K Samadi
IEEE Transactions on Semiconductor Manufacturing 22 (4), 552-565, 2009
532009
Accurate machine-learning-based on-chip router modeling
K Jeong, AB Kahng, B Lin, K Samadi
IEEE Embedded Systems Letters 2 (3), 62-66, 2010
512010
Interference assisted lithography for patterning of 1D gridded design
RT Greenway, R Hendel, K Jeong, AB Kahng, JS Petersen, Z Rao, ...
Alternative Lithographic Technologies 7271, 741-751, 2009
442009
MAPG: Memory access power gating
K Jeong, AB Kahng, S Kang, TS Rosing, R Strong
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2012
352012
MAPG: Memory access power gating
K Jeong, AB Kahng, S Kang, TS Rosing, R Strong
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2012
352012
Timing yield-aware color reassignment and detailed placement perturbation for bimodal CD distribution in double patterning lithography
M Gupta, K Jeong, AB Kahng
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010
302010
Revisiting the linear programming framework for leakage power vs. performance optimization
K Jeong, AB Kahng, H Yao
2009 10th International Symposium on Quality Electronic Design, 127-134, 2009
302009
Timing analysis and optimization implications of bimodal CD distribution in double patterning lithography
K Jeong, AB Kahng
2009 Asia and South Pacific Design Automation Conference, 486-491, 2009
302009
Methodology from chaos in IC implementation
K Jeong, AB Kahng
2010 11th International Symposium on Quality Electronic Design (ISQED), 885-892, 2010
292010
A power-constrained MPU roadmap for the International Technology Roadmap for Semiconductors (ITRS)
K Jeong, AB Kahng
2009 International SoC Design Conference (ISOCC), 49-52, 2009
282009
Is overlay error more important than interconnect variations in double patterning?
K Jeong, AB Kahng, RO Topaloglu
Proceedings of the 11th international workshop on System level interconnect …, 2009
282009
Assessing chip-level impact of double patterning lithography
K Jeong, AB Kahng, RO Topaloglu
2010 11th International Symposium on Quality Electronic Design (ISQED), 122-130, 2010
262010
Quantified impacts of guardband reduction on design process outcomes
K Jeong, AB Kahng, K Samadi
9th International Symposium on Quality Electronic Design (isqed 2008), 790-797, 2008
212008
Timing yield-aware color reassignment and detailed placement perturbation for double patterning lithography
M Gupta, K Jeong, AB Kahng
Proceedings of the 2009 International Conference on Computer-Aided Design …, 2009
192009
Electrical metrics for lithographic line-end tapering
P Gupta, K Jeong, AB Kahng, CH Park
Photomask and Next-Generation Lithography Mask Technology XV 7028, 977-988, 2008
192008
MTCMOS flip-flop, circuit including the MTCMOS flip-flop, and method of forming the MTCMOS flip-flop
H Won, K Jeong, YH Kim, BH Lee
US Patent 7,453,300, 2008
162008
Double patterning layout design method
TJ Song, JH Park, K Jeong
US Patent 9,098,670, 2015
152015
Method of designing layout of semiconductor device
K Jeong
US Patent 9,811,626, 2017
102017
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