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Shyh-Jye Jou
Shyh-Jye Jou
Email confirmado em mail.nctu.edu.tw
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A single-ended disturb-free 9T subthreshold SRAM with cross-point data-aware write word-line structure, negative bit-line, and adaptive read operation timing tracing
MH Tu, JY Lin, MC Tsai, CY Lu, YJ Lin, MH Wang, HS Huang, KD Lee, ...
IEEE Journal of Solid-State Circuits 47 (6), 1469-1482, 2012
1792012
An LDPC decoder chip based on self-routing network for IEEE 802.16 e applications
CH Liu, SW Yen, CL Chen, HC Chang, CY Lee, YS Hsu, SJ Jou
IEEE Journal of Solid-State Circuits 43 (3), 684-694, 2008
1552008
Single-ended subthreshold SRAM with asymmetrical write/read-assist
MH Tu, JY Lin, MC Tsai, SJ Jou, CT Chuang
IEEE Transactions on Circuits and Systems I: Regular Papers 57 (12), 3039-3047, 2010
1382010
40 nm bit-interleaving 12T subthreshold SRAM with data-aware write-assist
YW Chiu, YH Hu, MH Tu, JK Zhao, YH Chu, SJ Jou, CT Chuang
IEEE Transactions on Circuits and Systems I: Regular Papers 61 (9), 2578-2585, 2014
1362014
Mixed-mode simulation and analog multilevel simulation
RA Saleh, SJ Jou, AR Newton
Springer Science & Business Media, 1994
991994
Low-error reduced-width Booth multipliers for DSP applications
SJ Jou, MH Tsai, YL Tsao
IEEE Transactions on Circuits and Systems I: Fundamental Theory and …, 2003
952003
Antiplatelet constituents of formosan Rubia akane
MI Chung, SJ Jou, TH Cheng, CN Lin, FN Ko, CM Teng
Journal of natural products 57 (2), 313-316, 1994
751994
A pipelined multiplier-accumulator using a high-speed, low-power static and dynamic full adder design
SJ Jou, CY Chen, EC Yang, CC Su
IEEE Journal of solid-state circuits 32 (1), 114-118, 1997
641997
A 5.79-Gb/s energy-efficient multirate LDPC codec chip for IEEE 802.15. 3c applications
SW Yen, SY Hung, CL Chen, HC Chang, SJ Jou, CY Lee
IEEE journal of solid-state circuits 47 (9), 2246-2257, 2012
592012
All-digital synchronization for SC/OFDM mode of IEEE 802.15. 3c and IEEE 802.11 ad
WC Liu, TC Wei, YS Huang, CD Chan, SJ Jou
IEEE Transactions on Circuits and Systems I: Regular Papers 62 (2), 545-553, 2014
552014
A well-structured modified Booth multiplier design
LR Wang, SJ Jou, CL Lee
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI …, 2008
522008
Low switching noise and load-adaptive output buffer design techniques
SJ Jou, SH Kuo, JT Chiu, TH Lin
IEEE Journal of Solid-State Circuits 36 (8), 1239-1249, 2001
442001
On-chip voltage down converter for low-power digital system
SJ Jou, TL Chen
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 1998
431998
Design of a multimode QC-LDPC decoder based on shift-routing network
CH Liu, CC Lin, SW Yen, CL Chen, HC Chang, CY Lee, YS Hsu, SJ Jou
IEEE Transactions on Circuits and Systems II: Express Briefs 56 (9), 734-738, 2009
412009
Flavonol Glycosides and Cytotoxic Triterpenoids from Alphitonia Philippinensis
SJ Jou, CH Chen, JH Guh, CN Lee, SS Lee
Journal of the Chinese Chemical Society 51 (4), 827-834, 2004
402004
Continuous-flow parallel bit-reversal circuit for MDF and MDC FFT architectures
SG Chen, SJ Huang, M Garrido, SJ Jou
IEEE Transactions on Circuits and Systems I: Regular Papers 61 (10), 2869-2877, 2014
392014
A 40 nm 512 kb cross-point 8 T pipeline SRAM with binary word-line boosting control, ripple bit-line and adaptive data-aware write-assist
NC Lien, LW Chu, CH Chen, HI Yang, MH Tu, PS Kan, YJ Hu, CT Chuang, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 61 (12), 3416-3425, 2014
382014
8T single-ended sub-threshold SRAM with cross-point data-aware write operation
YW Chiu, JY Lin, MH Tu, SJ Jou, CT Chuang
IEEE/ACM International Symposium on Low Power Electronics and Design, 169-174, 2011
382011
Simultaneous switching noise analysis and low-bounce buffer design
SJ Jou, WC Cheng, YT Lin
IEE Proceedings-Circuits, Devices and Systems 148 (6), 303-311, 2001
372001
A design flow for multiplierless linear-phase FIR filters: From system specification to verilog code
KY Jheng, SJ Jou, AY Wu
2004 IEEE International Symposium on Circuits and Systems (ISCAS) 5, V-V, 2004
312004
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