Kevin D Jones
Title
Cited by
Cited by
Year
Larch: languages and tools for formal specification
JV Guttag, JJ Horning
Springer Science & Business Media, 2012
11342012
Mural: a formal development support system
CB Jones, KD Jones, P Lindsay, RD Moore
Springer Science & Business Media, 2012
2452012
Multi-functional Bi-directional Communication and Bias Power Architecture for Power Supply Control
GC Pabon, KD Jones, CY Ko, G Lagui, P Mody, ME Walsh, H Yu, ...
US Patent App. 12/772,165, 2010
532010
Fast, non-monte-carlo estimation of transient performance variation due to device mismatch
J Kim, KD Jones, MA Horowitz
IEEE Transactions on Circuits and Systems I: Regular Papers 57 (7), 1746-1755, 2009
462009
Analog property checkers: a DDR2 case study
KD Jones, V Konrad, D Ničković
Formal Methods in System Design 36 (2), 114-130, 2010
422010
LM3: A Larch interface language for Modula-3: A Definition and introduction
KD Jones
Systems Research Center, DEC, 1991
42*1991
MaCRA: a model-based framework for maritime cyber-risk assessment
K Tam, K Jones
WMU Journal of Maritime Affairs 18 (1), 129-163, 2019
352019
Cyber-risk assessment for autonomous ships
K Tam, K Jones
2018 International Conference on Cyber Security and Protection of Digital …, 2018
322018
Threats and impacts in maritime cyber security
KD Jones, K Tam, M Papadaki
IET, 2016
312016
Some “real world” problems in the analog and mixed signal domains,”
KD Jones, J Kim, V Konrad
Proceedings of Designing Correct Circuits, 51-68, 2008
302008
Transforming variable domains for linear circuit analysis
J Kim, KD Jones, M Horowitz
US Patent 8,185,853, 2012
262012
Method for using an equivalence checker to reduce verification effort in a system having analog blocks
KM Mossawir, KD Jones
US Patent 8,117,576, 2012
242012
Maritime cybersecurity policy: the scope and impact of evolving technology on international shipping
K Tam, KD Jones
Journal of Cyber Policy 3 (2), 147-164, 2018
232018
The automatic generation of functional test vectors for Rambus designs
KD Jones, JP Privitera
33rd Design Automation Conference Proceedings, 1996, 415-420, 1996
231996
Variable domain transformation for linear PAC analysis of mixed-signal systems
J Kim, KD Jones, MA Horowitz
2007 IEEE/ACM International Conference on Computer-Aided Design, 887-894, 2007
202007
Method to analyze an analog circuit design with a verification program
Q Hong, KD Jones, P Wong
US Patent 7,643,979, 2010
152010
LCL: A Larch interface language for C
JV Guttag, JJ Horning, SJ Garland, KD Jones, A Modet, JM Wing
Larch: Languages and Tools for Formal Specification, 56-101, 1993
121993
Factors Affecting Cyber Risk in Maritime
K Tam, K Jones
2019 International Conference on Cyber Situational Awareness, Data Analytics …, 2019
11*2019
Multi-format consistency checking tool
Q Hong, J Jiang, KD Jones, KM Mossawir, TJ Sheffler, P Wong
US Patent 7,392,492, 2008
112008
Noise Model Method of Predicting Mismatch Effects on Transient Circuit Behaviors
J Kim, MA Horowitz, KD Jones
US Patent App. 12/528,616, 2010
92010
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