| Towards acceleration of fault simulation using graphics processing units K Gulati, SP Khatri Proceedings of the 45th Annual Design Automation Conference, 822-827, 2008 | 147 | 2008 |
| Fast circuit simulation on graphics processing units K Gulati, JF Croix, SP Khatri, R Shastry 2009 Asia and South Pacific Design Automation Conference, 403-408, 2009 | 99 | 2009 |
| Accelerating statistical static timing analysis using graphics processing units K Gulati, SP Khatri 2009 Asia and South Pacific Design Automation Conference, 260-265, 2009 | 81 | 2009 |
| Hardware acceleration of EDA algorithms K Gulati, SP Khatri Springer, 2010 | 39 | 2010 |
| FPGA-based hardware acceleration for Boolean satisfiability K Gulati, S Paul, SP Khatri, S Patil, A Jas ACM Transactions on Design Automation of Electronic Systems (TODAES) 14 (2 …, 2009 | 38 | 2009 |
| Advanced Techniques in Logic Synthesis, Optimizations and Applications SP Khatri, K Gulati Springer, 2011 | 36 | 2011 |
| Boolean satisfiability on a graphics processor K Gulati, SP Khatri Proceedings of the 20th symposium on Great lakes symposium on VLSI, 123-126, 2010 | 25 | 2010 |
| Fault table computation on GPUs K Gulati, SP Khatri Journal of Electronic Testing 26, 195-209, 2010 | 24 | 2010 |
| Efficient, scalable hardware engine for Boolean satisfiability and unsatisfiable core extraction K Gulati, M Waghmode, SP Khatri, W Shi IET Computers & Digital Techniques 2 (3), 214-229, 2008 | 22 | 2008 |
| Network coding for routability improvement in VLSI N Jayakumar, SP Khatri, K Gulati, A Sprintson Proceedings of the 2006 IEEE/ACM international conference on Computer-aided …, 2006 | 17 | 2006 |
| A structured ASIC design approach using pass transistor logic K Gulati, N Jayakumar, SP Khatri 2007 IEEE International Symposium on Circuits and Systems, 1787-1790, 2007 | 16 | 2007 |
| Minimizing and exploiting leakage in VLSI design N Jayakumar, S Paul, R Garg Springer Science & Business Media, 2009 | 14 | 2009 |
| A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations K Gulati, N Jayakumar, SP Khatri, DMH Walker Integration 41 (3), 399-412, 2008 | 12 | 2008 |
| Fault table generation using graphics processing units K Gulati, SP Khatri 2009 IEEE International High Level Design Validation and Test Workshop, 60-67, 2009 | 11 | 2009 |
| GPU architecture and the CUDA programming model K Gulati, SP Khatri, K Gulati, SP Khatri Hardware Acceleration of EDA Algorithms: Custom ICs, FPGAs and GPUs, 23-30, 2010 | 10 | 2010 |
| Improving FPGA routability using network coding K Gulati, SP Khatri Proceedings of the 18th ACM Great Lakes symposium on VLSI, 147-150, 2008 | 10 | 2008 |
| Accelerating boolean satisfiability on a custom ic K Gulati, SP Khatri, K Gulati, SP Khatri Hardware Acceleration of EDA Algorithms: Custom ICs, FPGAs and GPUs, 33-61, 2010 | 8 | 2010 |
| Highly parallel decoding of space-time codes on graphics processing units KC Bollapalli, Y Wu, K Gulati, S Khatri, AR Calderbank 2009 47th Annual Allerton Conference on Communication, Control, and …, 2009 | 8 | 2009 |
| An efficient, scalable hardware engine for Boolean satisfiability M Waghmode, K Gulati, SP Khatri, W Shi 2006 International Conference on Computer Design, 326-331, 2006 | 7 | 2006 |
| A probabilistic method to determine the minimum leakage vector for combinational designs K Gulati, N Jayakumar, SP Khatri 2006 IEEE International Symposium on Circuits and Systems, 4 pp.-2244, 2006 | 7 | 2006 |
Weiping ShiProfessor of Electrical and Computer Engineering, Texas A&M UniversityVerified email at ece.tamu.edu
