Horacio Neto
Horacio Neto
INESC-ID / IST, University of Lisbon
Email confirmado em inesc-id.pt - Página inicial
TítuloCitado porAno
Macro-based hardware compilation of Java< sup> TM</sup> bytecodes into a dynamic reconfigurable computing system
JMP Cardoso, HC Neto
Field-Programmable Custom Computing Machines, 1999. FCCM'99. Proceedings …, 1999
1261999
Compilation for FPGA-based reconfigurable hardware
JMP Cardoso, HC Neto
IEEE Design & Test of Computers 20 (2), 65-75, 2003
752003
An exact solution to the minimum size test pattern problem
PF Flores, H Neto, JP Marques Silva
International Conference on Computer Design: VLSI in Computers and …, 1998
721998
Assignment and reordering of incompletely specified pattern sequences targetting minimum power dissipation
P Flores, J Costa, H Neto, J Monteiro, J Marques-Silva
Proceedings Twelfth International Conference on VLSI Design.(Cat. No …, 1999
581999
Recursos genéticos de Passiflora
FR Ferreira
Maracujá: germoplasma e melhoramento genético, 41-50, 2005
502005
An enhanced static-list scheduling algorithm for temporal partitioning onto RPUs
JMP Cardoso, HC Neto
VLSI: Systems on a Chip, 485-496, 2000
402000
Sorting units for FPGA-based embedded systems
R Marcelino, H Neto, JMP Cardoso
IFIP Working Conference on Distributed and Parallel Embedded Systems, 11-22, 2008
392008
Trends of CPU, GPU and FPGA for high-performance computing
M Vestias, H Neto
2014 24th International Conference on Field Programmable Logic and …, 2014
342014
Decimal multiplier on FPGA using embedded binary multipliers
HC Neto, MP Véstias
2008 International Conference on Field Programmable Logic and Applications …, 2008
342008
On applying set covering models to test set compaction
PF Flores, HC Neto, JP Marques-Silva
Proceedings Ninth Great Lakes Symposium on VLSI, 8-11, 1999
311999
Parallel decimal multipliers using binary multipliers
MP Véstias, HC Neto
2010 VI Southern Programmable Logic Conference (SPL), 73-78, 2010
292010
Towards an automatic path from Java< sup> TM</sup> bytecodes to hardware through high-level synthesis
JMP Cardoso, HC Neto
Electronics, Circuits and Systems, 1998 IEEE International Conference on 1 …, 1998
261998
Area and performance optimization of a generic network-on-chip architecture
MP Véstias, HC Neto
Proceedings of the 19th annual symposium on Integrated circuits and systems …, 2006
222006
Double-precision gauss-jordan algorithm with partial pivoting on fpgas
R Duarte, H Neto, M Véstias
2009 12th Euromicro Conference on Digital System Design, Architectures …, 2009
212009
An efficient and scalable architecture for neural networks with backpropagation learning
PO Domingos, FM Silva, HC Neto
International Conference on Field Programmable Logic and Applications, 2005 …, 2005
212005
Co-synthesis of a configurable SoC platform based on a network on chip architecture
MP Véstias, HC Neto
Proceedings of the 2006 Asia and South Pacific Design Automation Conference …, 2006
202006
On reconfigurable architectures for efficient matrix inversion
GM De Matos, HC Neto
2006 International Conference on Field Programmable Logic and Applications, 1-6, 2006
192006
A comparison of three representative hardware sorting units
R Marcelino, HC Neto, JMP Cardoso
2009 35th Annual Conference of IEEE Industrial Electronics, 2805-2810, 2009
182009
Bitwise encoding of finite state machines
J Monteiro, J Kukula, S Devadas, H Neto
Proceedings of 7th International Conference on VLSI Design, 379-382, 1994
181994
Iterative decimal multiplication using binary arithmetic
MP Véstias, HC Neto
2011 VII Southern Conference on Programmable Logic (SPL), 257-262, 2011
152011
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