V Ramgopal Rao, Fellow of IEEE, TWAS, INSA, INAE, IASc, NASI
V Ramgopal Rao, Fellow of IEEE, TWAS, INSA, INAE, IASc, NASI
Other namesV R Rao, Valipe Ramgopal Rao, Ramgopal Rao
IIT Bombay/IIT Delhi
Verified email at - Homepage
Cited by
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The impact of high-/spl kappa/gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs
B Cheng, M Cao, R Rao, A Inani, PV Voorde, WM Greene, JMC Stork, ...
IEEE Transactions on Electron Devices 46 (7), 1537-1544, 1999
A Tunnel FET forScaling Below 0.6 V With a CMOS-Comparable Performance
R Asra, M Shrivastava, KVRM Murali, RK Pandey, H Gossner, VR Rao
IEEE Transactions on Electron Devices 58 (7), 1855-1863, 2011
Fabrication and Analysis of a Heterojunction Line Tunnel FET
AM Walke, A Vandooren, R Rooyackers, D Leonelli, A Hikavyy, R Loo, ...
IEEE Transactions on Electron Devices 61 (3), 707-715, 2014
Noise in Drain and Gate Current of MOSFETs With High- Gate Stacks
P Magnone, F Crupi, G Giusi, C Pace, E Simoen, C Claeys, L Pantisano, ...
IEEE Transactions on Device and Materials Reliability 9 (2), 180-189, 2009
Polymer nanocomposite nanomechanical cantilever sensors: material characterization, device development and application in explosive vapour detection
V Seena, A Fernandes, P Pant, S Mukherji, VR Rao
Nanotechnology 22 (29), 295501, 2011
Gate fringe-induced barrier lowering in underlap FinFET structures and its optimization
AB Sachid, CR Manoj, DK Sharma, VR Rao
IEEE Electron Device Letters 29 (1), 128-130, 2007
Insights into the design and optimization of tunnel-FET devices and circuits
A Pal, AB Sachid, H Gossner, VR Rao
IEEE Transactions on Electron devices 58 (4), 1045-1053, 2011
NBTI degradation and its impact for analog circuit reliability
NK Jha, PS Reddy, DK Sharma, VR Rao
IEEE Transactions on Electron Devices 52 (12), 2609-2615, 2005
Impact of High- Gate Dielectrics on the Device and Circuit Performance of Nanoscale FinFETs
CR Manoj, VR Rao
IEEE electron device letters 28 (4), 295-297, 2007
Physical insight toward heat transport and an improved electrothermal modeling framework for FinFET architectures
M Shrivastava, M Agrawal, S Mahajan, H Gossner, T Schulz, DK Sharma, ...
IEEE Transactions on Electron Devices 59 (5), 1353-1363, 2012
Impact of halo doping on the subthreshold performance of deep-submicrometer CMOS devices and circuits for ultralow power analog/mixed-signal applications
S Chakraborty, A Mallik, CK Sarkar, VR Rao
IEEE Transactions on Electron Devices 54 (2), 241-248, 2007
Organic field effect transistors (OFETs) in environmental sensing and health monitoring: A review
SG Surya, HN Raval, R Ahmad, P Sonar, KN Salama, VR Rao
TrAC Trends in Analytical Chemistry 111, 27-36, 2019
Silanization and antibody immobilization on SU-8
M Joshi, R Pinto, VR Rao, S Mukherji
Applied surface science 253 (6), 3127-3132, 2007
The effect of high-k gate dielectrics on deep submicrometer CMOS device and circuit performance
NR Mohapatra, MP Desai, SG Narendra, VR Rao
IEEE transactions on electron devices 49 (5), 826-831, 2002
DC compact model for SOI tunnel field-effect transistors
B Bhushan, K Nayak, VR Rao
IEEE transactions on electron devices 59 (10), 2635-2642, 2012
A novel dry method for surface modification of SU-8 for immobilization of biomolecules in Bio-MEMS
M Joshi, N Kale, R Lal, VR Rao, S Mukherji
Biosensors and Bioelectronics 22 (11), 2429-2435, 2007
An ultra-sensitive piezoresistive polymer nano-composite microcantilever sensor electronic nose platform for explosive vapor detection
SJ Patil, N Duragkar, VR Rao
Sensors and Actuators B: Chemical 192, 444-451, 2014
Device design and optimization considerations for bulk FinFETs
CR Manoj, M Nagpal, D Varghese, VR Rao
IEEE transactions on electron devices 55 (2), 609-615, 2008
Sub-20 nm gate length FinFET design: Can high-κ spacers make a difference?
AB Sachid, R Francis, MS Baghini, DK Sharma, KH Bach, R Mahnkopf, ...
2008 IEEE International Electron Devices Meeting, 1-4, 2008
Semiconductor devices
H Gossner, R Rao, A Sachid, A Pal, R Asra
US Patent 8,405,121, 2013
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