| Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology P Flatresse, B Giraud, JP Noel, B Pelloux-Prayer, F Giner, DK Arora, ... 2013 IEEE International Solid-State Circuits Conference Digest of Technical …, 2013 | 88 | 2013 |
| Logical effort model extension to propagation delay representation B Lasbouygues, S Engels, R Wilson, P Maurine, N Azémard, D Auvergne IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006 | 47 | 2006 |
| A predictive bottom-up hierarchical approach to digital system reliability V Huard, E Pion, F Cacho, D Croain, V Robert, R Delater, P Mergault, ... 2012 IEEE International Reliability Physics Symposium (IRPS), 4B. 1.1-4B. 1.10, 2012 | 40 | 2012 |
| Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs E Beigné, A Valentian, B Giraud, O Thomas, T Benoist, Y Thonnart, ... 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 613-618, 2013 | 37 | 2013 |
| Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec J Le Coz, P Flatresse, S Engels, A Valentian, M Belleville, C Raynaud, ... 2011 IEEE International Solid-State Circuits Conference, 336-337, 2011 | 15 | 2011 |
| A simple statistical timing analysis flow and its application to timing margin evaluation V Migairou, R Wilson, S Engels, Z Wu, N Azemard, P Maurine International Workshop on Power and Timing Modeling, Optimization and …, 2007 | 13 | 2007 |
| A fine grain variation-aware dynamic Vdd-hopping AVFS architecture on a 32nm GALS MPSoC E Beigné, I Miro-Panades, Y Thonnart, L Alacoque, P Vivet, S Lesecq, ... 2013 Proceedings of the ESSCIRC (ESSCIRC), 57-60, 2013 | 9 | 2013 |
| Dual-edge register and the monitoring thereof on the basis of a clock S Engels US Patent 8,436,652, 2013 | 8 | 2013 |
| An event-based strategy for ASK demodulation ARI Jadue, S Engels, L Fesquet 2019 5th International Conference on Event-Based Control, Communication, and …, 2019 | 6 | 2019 |
| Bottom-up digital system-level reliability modeling NR Amador, V Huard, E Pion, F Cacho, D Croain, V Robert, S Engels, ... 2011 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2011 | 6 | 2011 |
| A low-power 16-channel AD converter and digital processor ASIC D Subiela, S Engels, L Dugoujon, R Esteve-Bosch, B Mota, L Musa, ... Proceedings of the 28th European Solid-State Circuits Conference, 259-262, 2002 | 6 | 2002 |
| A comprehensive performance macro-modeling of on-chip RC interconnects considering line shielding effects S Engels, R Wilson, N Azémard, P Maurine Integration 39 (4), 433-456, 2006 | 5 | 2006 |
| A low–power 16–channel AD converter and digital processor ASIC B Mota, A Jimenez-de-Parga, L Musa, L Dugoujon, R Esteve-Bosch, ... | 5 | 2002 |
| Event-based design strategy for circuit electromagnetic compatibility S Germain, S Engels, L Fesquet 2017 3rd International Conference on Event-Based Control, Communication and …, 2017 | 4 | 2017 |
| Transistor substrate dynamic biasing circuit LE Julien, A Valentian, P Flatresse, S Engels US Patent 8,570,096, 2013 | 4 | 2013 |
| High Level Current Modeling for Shaping Electromagnetic Emissions in Micropipeline Circuits S Germain, S Engels, L Fesquet Journal of Low Power Electronics and Applications 9 (1), 6, 2019 | 3 | 2019 |
| Electronic circuit design method LE Julien, S Engels, A Tournier US Patent 8,819,615, 2014 | 3 | 2014 |
| Voltage scaling and body biasing methodology for high performance hardwired LDPC N Moubdi, P Maurine, R Wilson, N Azemard, S Engels, L Rolindez, ... 2010 IEEE International Conference on Integrated Circuit Design and …, 2010 | 3 | 2010 |
| A Distributed Body-Biasing Strategy for Asynchronous Circuits L Fesquet, Y Decoudu, ARI Jadue, TF de Paiva Leite, O Rolloff, M Diallo, ... 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration …, 2019 | 2 | 2019 |
| A 6-Wire Plug and Play Clockless Distributed On-Chip-Sensor Network in 28 nm UTBB FD-SOI M Renaudin, A Bouzafour, S Engels, R Wilson Journal of Low Power Electronics 14 (3), 404-413, 2018 | 2 | 2018 |
